Display controller to prevent visual artifacts with spread spectrum clocking

ABSTRACT

A display controller and method for performing the same operations are described. In on embodiment, the display controller comprises a spread spectrum clock (SSC) modulator having a first input coupled to receive a non-SSC modulated clock and operable to generate a SSC modulated clock in response to the non-SSC modulated clock, a video data transfer portion coupled to receive the SSC modulated clock and operable to output data for display in response to the SSC modulated clock, and a second portion coupled to receive the non-SSC modulated clock.

RELATED APPLICATIONS

This patent arises from a continuation of U.S. patent application Ser.No. 15/277,845, (now U.S. Pat. No. ______), which is titled “DISPLAYCONTROLLER TO PREVENT VISUAL ARTIFACTS WITH SPREAD SPECTRUM CLOCKING,”and which was filed on Sep. 27, 2016. Priority to U.S. patentapplication Ser. No. 15/277,845 is claimed. U.S. patent application Ser.No. 15/277,845 is hereby incorporated herein by reference in itsentirety.

FIELD OF THE DISCLOSURE

Embodiments of the present invention relate to the field of displaycontrollers for computing systems; more particularly, embodiments of thepresent invention relate to display controllers that use spread spectrumclocking to clock a portion of a display controller and another clock toclock other portions of a display controller.

BACKGROUND

A typical computer system uses clock signals to synchronize operationsof digital circuitry of the system. Unfortunately, spectral componentsof these clock signals may contribute to the radiation ofelectromagnetic interference (EMI) emissions from the system. The EMIemissions may cause undesirable interference with the circuitry of thecomputer system and other electronic equipment near the computer system.To reduce the EMI emissions outside of the computer system, thecircuitry of the computer system may be housed inside a metal casingthat prevents the EMI emissions from propagating outside of the casing.However, the casing often adds to the weight and cost of the computersystem, and the casing may have a limited EMI shielding capability.

The EMI emissions may be reduced by spread spectrum clocking (SSC), atechnique that reduces the energy peaks present in the spectralcomponents of the clock signal. In SSC, a spread spectrum clock signalmay be generated by an SSC generator. SSC is widely deployed in thevideo data transfer interface, such as low-voltage differentialsignaling (LVDS), Transition-minimized differential signaling (TMDS) andMobile Industry Processor Interface Display Serial Interface (MIPIDSI),in order to suppress its pixel clock (PCLK) oriented radio frequency(RF) emission and its interference to RF application. SSC usuallymodulates PCLK cycle. As the PCLK is the unit time of one pixel datatransfer, the SSC application moderates the video timing cycle, such asone horizontal (1H) line access cycle as well as one frame update cycle.In a certain display device application, such as, for example, ActiveMatrix organic light-emitting diode (OLED), the 1H cycle modulationcauses each line brightness variation, observed as the visual artifact.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousembodiments of the invention, which, however, should not be taken tolimit the invention to the specific embodiments, but are for explanationand understanding only.

FIG. 1 is a block diagram of a conventional display controller.

FIG. 2 is a block diagram of one embodiment of a display controller.

FIG. 3A is a flow diagram of one embodiment of a process for generatingdisplay data.

FIG. 3B is a flow diagram of one embodiment of the processor forgenerating display data using a video transfer portion clocked with aSSC modulated pixel clock

FIG. 4 is a block diagram of one embodiment of example data sources forvideo data being processed by a display controller.

FIG. 5 is a block diagram of one embodiment of a computer system.

DETAILED DESCRIPTION

In the following description, numerous details are set forth to providea more thorough explanation of the present invention. It will beapparent, however, to one skilled in the art, that the present inventionmay be practiced without these specific details. In other instances,well-known structures and devices are shown in block diagram form,rather than in detail, in order to avoid obscuring the presentinvention.

A display controller that prevents or substantially avoids producingvisual artifacts is disclosed. The display controller prevents suchartifacts by using spread spectrum clocking (SSC) for clocking some ofthe operations and/or portions of the display controller. Morespecifically, in one embodiment, the display controller includes twopixel clocks (PCLKs), one is the base clock without SSC modulation andthe other has been modulated with SSC modulation. In one embodiment, theSSC modulated PCLK is only applied to portions of the display controllerthat are involved with the video data transfer, while the non-SSCmodulated PCLK is applied to other portions of the display controller.In one embodiment, the other portions include a 1 horizontal (1H) cyclecounter, a counter reset, and a vertical synchronization (Vsync)counter. By using the non-SSC modulated clock, 1H cycle and one vertical(1V) frame access cycle are constant and not varied by SSC modulation.

By preventing 1H and 1V cycle from being modulated by SSC, any visualartifact caused by 1H or 1V modulation is suppressed. At the same time,the SSC modulation in PCLK as well as video data, which are the mainsource of RF emission as well as RF interference, causes suppression ofthe EMI issues.

In one embodiment, the display controller is part of a computer system.

To better explain novel features of embodiments of the displaycontroller disclosed herein, the disclosure initially describes aconventional display controller. FIG. 1 shows the conventional displaycontroller design with SSC modulation on PCLK. Referring to FIG. 1, avideo memory 101 (e.g., random access memory (RAM)) receives and storesvideo data. In one embodiment, video memory 101 is part of the displaycontroller. In another embodiment, video memory 101 is not part of thedisplay controller. The video data from video memory 101 is written tovideo first-in first-out (FIFO) memory 103 via memory transfers, suchas, for example, direct memory access (DMA) controller write operations102. In one embodiment, both FIFO 103 and DMA controller 102 are part ofthe display controller. The data from video FIFO memory 103 is output asvideo data 104 to data output enable 110.

A base pixel clock (PCLK) 105 is modulated by SSC modulator 106 based ona reference clock referred to herein as modulation clock (CLK) 107. TheSSC modulated PCLK is coupled to an input of H counter 108 as well as aclock input for Vsync signal generator (Vsync enable) 115. In responseto the SSC modulated PCLK, H counter 108 counts up and generates asignal to data output enable 110 in a manner well-known in the art tocause data output enable 110 to output a data enable (DE) signal 121 andvideo data 122 (e.g., D[23:0]) to a display (not shown).

The output signal from H counter 108 is also coupled to an input ofHorizontal synchronization (Hsync) signal generator (Hsync Enable) 121,which generates Hsync signal 123 in a manner well known in the art inresponse to the output signal from H counter 108. H counter reset signalgenerator 113 also includes an input coupled to receive the outputsignal from H counter 108 and generates a reset signal 109 that resets Hcounter 108 in a manner well known in the art.

The display controller also includes V counter 114 that has an inputcoupled to Hsync signal 123. In response to Hsync signal 123, V counter114 counts up and generates an output signal in a manner well known inthe art. The output signal from V counter 114 is coupled to an input ofVsync enable 115, which generates Vsync signal 125 in a manner wellknown in the art. The output of V counter 114 is also coupled to aninput of V counter reset signal generator 116, which generates a resetsignal 126 to reset V counter 114 in a manner well known in the art.

Thus, in FIG. 1, with SSC modulation on PCLK, the H sync cycle and the Vsync cycle are modulated together as the SSC modulated PCLK is used forH counter 108 and V counter 114 for the H and V related timing.

Similar to the display controller in FIG. 1, the display controllerdescribed herein includes a spread spectrum clock (SSC) modulator havinga first input coupled to receive the pixel clock and generates a SSCmodulated pixel clock in response to a non-SSC modulated pixel clock.However, in contrast, the display controller described herein includestwo portions, one of which is clocked by the SSC modulated pixel clockand the other that is clocked by the non-SSC modulated pixel clock. Inone embodiment, the video data transfer portion of the displaycontroller is clocked by and/or is responsive to the SSC modulated pixelclock and outputs data from the display controller for display inresponse to the SSC modulated pixel clock, while another portion of thedisplay controller receives, is clocked by, and/or is responsive to thenon-SSC modulated pixel clock. In one embodiment, this other portionincludes a second H counter, an H counter reset signal generator, aHsync signal generator (Hsync enable), V counter, and V counter resetsignal generator.

FIG. 2 is a block diagram of one embodiment of a display controller.Referring to FIG. 2, as in FIG. 1, a video memory 101 (e.g., randomaccess memory (RAM)) receives and stores video data. The video data fromvideo memory 101 is written to video first-in first-out (FIFO) memory103 via memory transfers, such as, for example, direct memory access(DMA) write operations 102. The data from video FIFO memory 103 isoutput as video data 104 to data output enable 110.

A base pixel clock (PCLK) 105 is modulated by SSC modulator 106 based ona reference clock referred to herein as modulation clock (CLK) 107. TheSSC modulated PCLK is coupled to an input of a first H counter, Hcounter 201. In response to the SSC modulated PCLK, H counter 201 countsup and generates a signal to data output enable 110 in a mannerwell-known in the art to cause data output enable 110 to output a dataenable (DE) signal 121 and video data 122 (e.g., D[23:0]) to a display(not shown).

A second H counter, H counter 202, is clocked by base PCLK 105 andcounts up in response to base PCLK 105. H counter 202 outputs a signalHsync signal generator (Hsync enable) 204, which generates Hsync signal210 in response to the output signal from H counter 202 in a manner wellknown in the art. In one embodiment, Hsync signal 210 is asserted when HCounter 201 (and H counter 202) is reset, so it follows the non-SSCmodulated timing.

H counter reset signal generator 203 also includes an input coupled toreceive the output signal from H counter 202 and generates a resetsignal 211 that resets both H counter 201 and H counter 202.

The display controller also includes V counter 205 that has an inputcoupled to Hsync signal 210. In response to Hsync signal 210, V counter205 counts up and generates an output signal in a manner well known inthe art. The output signal from V counter 205 is coupled to an input ofVsync signal generator (Vsync enable) 206. Vsync signal generator 206 isalso coupled to receive the non-SSC modulated clock. In response tothese inputs, Vsync signal generator 206 generates Vsync signal 212 in amanner well known in the art. Since the Vsync signal 212 is generated byV counter 205, which applies the Hsync signal 210 generated by H Counter202, it follows the non-SSC modulated PCLK timing.

The output of V counter 205 is also coupled to an input of V counterreset signal generator 207, which generates a reset signal 213 to resetV counter 205.

Thus, the display controller in FIG. 2 includes 2 H counters: H Counter201 and H Counter 202, where H Counter 201 applies the SSC modulatedPCLK as the count-up CLK, and H Counter 202 applies the base PCLK, whichis not SSC modulated. The video data transfer is correlated to H Counter201 so that it follows the SSC modulated PCLK timing. However, H counter201 is reset by a reset signal that is generated in response to anoutput of H counter 202, which is correlated to the non-SSC modulatedPCLK.

By having the high frequency components of the display controller (e.g.,components involved in the video data transfer) and other portions ofthe display controller (e.g., Hsync generation and at least part ofVsync generation), the display controller provides video data with goodvisual quality with no or a reduced number of artifacts, therebyavoiding any EMI issues related to the display interface.

FIG. 3A is a flow diagram of one embodiment of a process for generatingdisplay data. In one embodiment, the process is performed by processinglogic that may comprise hardware (circuitry, dedicated logic, etc.),software (such as is run on a general purpose computer system or adedicated machine), firmware, or a combination of the three.

Referring to FIG. 3A, the process begins by processing logic in thedisplay controller receiving and storing data for display (processingblock 301).

Also, a spread spectrum modulator modulates a pixel clock to generate aSSC modulated pixel clock (processing block 302). A video data transferportion of a display controller is clocked with the SSC modulated pixelclock to output data for display in response to the SSC modulated pixelclock (processing block 303).

Another portion of the display controller that is not part of the videodata transfer portion is clocked with the non-SSC modulated pixel clock,including clocking a second H counter in the second portion with anon-SSC modulated pixel clock (processing block 304).

Furthermore, a reset signal is generated in response to a first signalfrom the second H counter (processing block 305) and the first andsecond H counters are reset using the reset signal (processing block306).

Moreover, a horizontal synchronization (Hsync) signal is generated inresponse to an output of the second H counter (processing block 307)

A vertical synchronization (Vsync) signal is generated in response toHsync signal and the non-SSC modulated pixel clock, including generatinga first signal using a vertical (V) counter in response to the Hsyncsignal, wherein generating the Vsync signal occurs in response to thefirst signal (processing block 308).

FIG. 3B is a flow diagram of one embodiment of the processor forgenerating display data using a video transfer portion clocked with aSSC modulated pixel clock. In one embodiment, the process is performedby processing logic that may comprise hardware (circuitry, dedicatedlogic, etc.), software (such as is run on a general purpose computersystem or a dedicated machine), firmware, or a combination of the three.

Referring to FIG. 3B, the process includes clocking a first horizontal(H) counter in the video data transfer portion with the SSC modulatedpixel clock (processing block 311). Next, the horizontal (H) countercounts up and outputs a signal in response to the SSC modulated pixelclock (processing block 312). In response to the signal from the Hcounter, a data output enable outputs, for display, data received by thedisplay controller and stored in a display controller memory (e.g.,FIFO) (processing block 313).

FIG. 4 is a block diagram of one embodiment of example data sources forvideo data being processed by a display controller. Referring to FIG. 4,data for display are generated by a video decoder 401 (e.g., videocodec) and graphics processing unit 402, and stored in frame buffers 403and 404, respectively, which are part of main memory. The stored Acomposer 405 combines the data from frame buffers 403 and 404 togenerate a composited output frame that is stored in frame buffer 406,which is part of main memory. The stored composited output frame is readfrom frame buffer 406 by display controller 407. Display controller 407clocks portions with a SSC modulated clock and other portions with anon-SSC modulated clock. Display controller 407 sends the compositedoutput frame to a display 408 for display.

FIG. 5 is one embodiment of a system level diagram 500 that mayincorporate the techniques described above. For example, the techniquesdescribed above may be used in conjunction with a processor in system500 or other part of system 500.

Referring to FIG. 5, system 500 includes, but is not limited to, adesktop computer, a laptop computer, a netbook, a tablet, a notebookcomputer, a personal digital assistant (PDA), a server, a workstation, acellular telephone, a mobile computing device, a smart phone, anInternet appliance or any other type of computing device. In anotherembodiment, system 500 implements the methods disclosed herein and maybe a system on a chip (SOC) system.

In one embodiment, processor 510 has one or more processor cores 512 to512N, where 512N represents the Nth processor core inside the processor510 where N is a positive integer. In one embodiment, system 500includes multiple processors including processors 510 and 505, whereprocessor 505 has logic similar or identical to logic of processor 510.In one embodiment, system 500 includes multiple processors includingprocessors 510 and 505 such that processor 505 has logic that iscompletely independent from the logic of processor 510. In such anembodiment, a multi-package system 500 is a heterogeneous multi-packagesystem because the processors 505 and 510 have different logic units. Inone embodiment, processing core 512 includes, but is not limited to,pre-fetch logic to fetch instructions, decode logic to decode theinstructions, execution logic to execute instructions and the like. Inone embodiment, processor 510 has a cache memory 516 to cacheinstructions and/or data of the system 500. In another embodiment of theinvention, cache memory 516 includes level one, level two and levelthree, cache memory, or any other configuration of the cache memorywithin processor 510.

In one embodiment, processor 510 includes a memory control hub (MCH)514, which is operable to perform functions that enable processor 510 toaccess and communicate with a memory 530 that includes a volatile memory532 and/or a non-volatile memory 534. In one embodiment, memory controlhub (MCH) 514 is positioned outside of processor 510 as an independentintegrated circuit.

In one embodiment, processor 510 is operable to communicate with memory530 and a chipset 520. In such an embodiment, SSD 580 executes thecomputer-executable instructions when SSD 580 is powered up.

In one embodiment, processor 510 is also coupled to a wireless antenna578 to communicate with any device configured to transmit and/or receivewireless signals. In one embodiment, wireless antenna interface 578operates in accordance with, but is not limited to, the IEEE 802.11standard and its related family, HomePlug AV (HPAV), Ultra Wide Band(UWB), Bluetooth, WiMAX, or any form of wireless communication protocol.

In one embodiment, the volatile memory 532 includes, but is not limitedto, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic RandomAccess Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM),and/or any other type of random access memory device. Non-volatilememory 534 includes, but is not limited to, flash memory (e.g., NAND,NOR), phase change memory (PCM), read-only memory (ROM), electricallyerasable programmable read-only memory (EEPROM), or any other type ofnon-volatile memory device.

Memory 530 stores information and instructions to be executed byprocessor 510. In one embodiment, chipset 520 connects with processor510 via Point-to-Point (PtP or P-P) interfaces 517 and 522. In oneembodiment, chipset 520 enables processor 510 to connect to othermodules in the system 500. In one embodiment, interfaces 517 and 522operate in accordance with a PtP communication protocol such as theIntel QuickPath Interconnect (QPI) or the like.

In one embodiment, chipset 520 is operable to communicate with processor510, 505, display device 540, and other devices 572, 576, 574, 560, 562,564, 566, 577, etc. In one embodiment, chipset 520 is also coupled to awireless antenna 578 to communicate with any device configured totransmit and/or receive wireless signals.

In one embodiment, chipset 520 connects to a display device 540 via aninterface 526. In one embodiment, display device 540 includes, but isnot limited to, liquid crystal display (LCD), plasma, cathode ray tube(CRT) display, or any other form of visual display device. In addition,chipset 520 connects to one or more buses 550 and 555 that interconnectvarious modules 574, 560, 562, 564, and 566. In one embodiment, buses550 and 555 may be interconnected together via a bus bridge 572 if thereis a mismatch in bus speed or communication protocol. In one embodiment,chipset 520 couples with, but is not limited to, a non-volatile memory560, a mass storage device(s) 562, a keyboard/mouse 564, and a networkinterface 566 via interface 524, smart TV 576, consumer electronics 577,etc.

In one embodiment, mass storage device 562 includes, but is not limitedto, a solid state drive, a hard disk drive, a universal serial bus flashmemory drive, or any other form of computer data storage medium. In oneembodiment, network interface 566 is implemented by any type ofwell-known network interface standard including, but not limited to, anEthernet interface, a universal serial bus (USB) interface, a PeripheralComponent Interconnect (PCI) Express interface, a wireless interfaceand/or any other suitable type of interface.

While the modules shown in FIG. 5 are depicted as separate blocks withinthe system 500, the functions performed by some of these blocks may beintegrated within a single semiconductor circuit or may be implementedusing two or more separate integrated circuits.

In a first example embodiment, a display controller comprises a spreadspectrum clock (SSC) modulator having a first input coupled to receive anon-SSC modulated clock and operable to generate a SSC modulated clockin response to the non-SSC modulated clock, a video data transferportion coupled to receive the SSC modulated clock and operable tooutput data for display in response to the SSC modulated clock, and asecond portion coupled to receive the non-SSC modulated clock.

In another example embodiment, the subject matter of the first exampleembodiment can optionally include first and second horizontal (H)counters, the first H counter coupled to receive the SSC modulated clockand being in the video data transfer portion and the second H countercoupled to receive the non-SSC modulated clock and being in the secondportion. In another example embodiment, the subject matter of thisexample embodiment can optionally include an H counter reset generatorcoupled to the first and second H counters and responsive to an outputof the second H counter to generate a reset signal to reset the firstand second H counters. In another example embodiment, the subject matterof that example embodiment can optionally include a horizontalsynchronization (Hsync) signal generator coupled to an output of thesecond H counter and operable to generate a Hsync signal in response tothe output of the second H counter. In another example embodiment, thesubject matter of this example embodiment can optionally include that avertical synchronization (Vsync) signal generator operable to generate aVsync signal in response to Hsync signal and the non-SSC modulatedclock. In another example embodiment, the subject matter of this exampleembodiment can optionally include a vertical (V) counter coupled toreceive the Hsync signal and operable to output a first signal inresponse to the Hsync signal, where the Vsync signal generator has asecond input coupled to receive the first signal and operable togenerate the Vsync signal in response to the first signal.

In another example embodiment, the subject matter of the first exampleembodiment can optionally include that the video data transfer portioncomprises a memory coupled to receive data for display, a horizontal (H)counter coupled to receive the SSC modulated clock and operable tooutput a second signal in response to the SSC modulated clock, and adata output enable coupled to receive the count signal and the memoryand operable to output, for display, data from the memory in response tothe second signal.

In a second example embodiment, a system comprises a display; aprocessor operable to generate data for the display; and a displaycontroller coupled to the processor and the display, where the displaycontroller comprises a spread spectrum clock (SSC) modulator having afirst input coupled to receive a non-SSC modulated clock and operable togenerate a SSC modulated clock in response to the non-SSC modulatedclock, a video data transfer portion coupled to receive the SSCmodulated clock and operable to output data for display in response tothe SSC modulated clock, and a second portion coupled to receive thenon-SSC modulated clock.

In another example embodiment, the subject matter of the second exampleembodiment can optionally include first and second horizontal (H)counters, the first H counter coupled to receive the SSC modulated clockand being in the video data transfer portion and the second H countercoupled to receive the non-SSC modulated clock and being in the secondportion. In another example embodiment, the subject matter of thisexample embodiment can optionally include an H counter reset generatorcoupled to the first and second H counters and responsive to an outputof the second H counter to generate a reset signal to reset the firstand second H counters. In another example embodiment, the subject matterof that example embodiment can optionally include a horizontalsynchronization (Hsync) signal generator coupled to an output of thesecond H counter and operable to generate a Hsync signal in response tothe output of the second H counter. In another example embodiment, thesubject matter of the second example embodiment can optionally include avertical synchronization (Vsync) signal generator operable to generate aVsync signal in response to Hsync signal and the non-SSC modulatedclock. In another example embodiment, the subject matter of this exampleembodiment can optionally include that a vertical (V) counter coupled toreceive the Hsync signal and operable to output a first signal inresponse to the Hsync signal, where the Vsync signal generator has asecond input coupled to receive the first signal and operable togenerate the Vsync signal in response to the first signal. In anotherexample embodiment, the subject matter of this example embodiment canoptionally include that the video data transfer portion comprises amemory coupled to receive data for display, a horizontal (H) countercoupled to receive the SSC modulated clock and operable to output asecond signal in response to the SSC modulated clock, and a data outputenable coupled to the display and the memory and to receive the secondsignal, the data output enable being operable to output, for display onthe display, data from the memory in response to the second signal.

In another example embodiment, the subject matter of the second exampleembodiment can optionally include that the processor comprises a videodecoder and a graphics processing unit to generate the data for thedisplay.

In a third example embodiment, a method comprises modulating a clockwith a spread spectrum clock (SSC) modulator to generate a SSC modulatedclock, clocking a video data transfer portion of a display controllerwith the SSC modulated clock to output data for display in response tothe SSC modulated clock, and clocking a second portion of the displaycontroller with the non-SSC modulated clock.

In another example embodiment, the subject matter of the third exampleembodiment can optionally include clocking a first horizontal (H)counter in the video data transfer portion with the SSC modulated clockand clocking a second H counter in the second portion with a non-SSCmodulated clock. In another example embodiment, the subject matter ofthis example embodiment can optionally include generating a reset signalin response to a first signal from the second H counter and resettingthe first and second H counters using the reset signal. In anotherexample embodiment, the subject matter of that example embodiment canoptionally include generating a horizontal synchronization (Hsync)signal in response to an output of the second H counter. In anotherexample embodiment, the subject matter of this example embodiment canoptionally include generating a vertical synchronization (Vsync) signalin response to Hsync signal and the non-SSC modulated clock. In anotherexample embodiment, the subject matter of this example embodiment canoptionally include generating a first signal using a vertical (V)counter in response to the Hsync signal, wherein generating the Vsyncsignal occurs in response to the first signal.

In another example embodiment, the subject matter of the second exampleembodiment can optionally include storing in a memory data for displayreceived by the display controller, outputting a first signal inresponse to the SSC modulated clock using a horizontal (H) counter, andoutputting, for display and in response to the first signal, datareceived from the memory.

Some portions of the detailed descriptions which follow are presented interms of algorithms and symbolic representations of operations on databits within a computer memory. These algorithmic descriptions andrepresentations are the means used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of steps leading to a desiredresult. The steps are those requiring physical manipulations of physicalquantities. Usually, though not necessarily, these quantities take theform of electrical or magnetic signals capable of being stored,transferred, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. Unlessspecifically stated otherwise as apparent from the following discussion,it is appreciated that throughout the description, discussions utilizingterms such as “processing” or “computing” or “calculating” or“determining” or “displaying” or the like, refer to the action andprocesses of a computer system, or similar electronic computing device,that manipulates and transforms data represented as physical(electronic) quantities within the computer system's registers andmemories into other data similarly represented as physical quantitieswithin the computer system memories or registers or other suchinformation storage, transmission or display devices.

The present invention also relates to apparatus for performing theoperations herein. This apparatus may be specially constructed for therequired purposes, or it may comprise a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program may be stored in a computerreadable storage medium, such as, but is not limited to, any type ofdisk including floppy disks, optical disks, CD-ROMs, andmagnetic-optical disks, read-only memories (ROMs), random accessmemories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any typeof media suitable for storing electronic instructions, and each coupledto a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general purposesystems may be used with programs in accordance with the teachingsherein, or it may prove convenient to construct more specializedapparatus to perform the required method steps. The required structurefor a variety of these systems will appear from the description below.In addition, the present invention is not described with reference toany particular programming language. It will be appreciated that avariety of programming languages may be used to implement the teachingsof the invention as described herein.

A machine-readable medium includes any mechanism for storing ortransmitting information in a form readable by a machine (e.g., acomputer). For example, a machine-readable medium includes read onlymemory (“ROM”); random access memory (“RAM”); magnetic disk storagemedia; optical storage media; flash memory devices; etc.

Whereas many alterations and modifications of the present invention willno doubt become apparent to a person of ordinary skill in the art afterhaving read the foregoing description, it is to be understood that anyparticular embodiment shown and described by way of illustration is inno way intended to be considered limiting. Therefore, references todetails of various embodiments are not intended to limit the scope ofthe claims which in themselves recite only those features regarded asessential to the invention.

1. (canceled)
 2. A display controller comprising: a clock generator togenerate a modulated clock based on a base clock; first logic circuitryto be clocked by the modulated clock, the first logic circuitryincluding a first counter to be clocked by the modulated clock, thefirst logic circuitry to output an enable signal based on the firstcounter, the enable signal associated with transfer of video data to adisplay; and second logic circuitry to be clocked by the base clock, thesecond logic circuitry including a second counter to be clocked by thebase clock, the second logic circuitry to output a synchronizationsignal based on the second counter, the synchronization signal to definea horizontal line access cycle, the second logic circuitry to reset thefirst counter and the second counter based on the base clock.
 3. Thedisplay controller of claim 2, wherein the modulated clock is a spreadspectrum clock, and the base clock is unmodulated.
 4. The displaycontroller of claim 2, wherein the synchronization signal is a firstsynchronization signal and the second logic circuitry is to output asecond synchronization signal based on the first synchronization signal,the second synchronization signal to define a vertical frame accesscycle.
 5. The display controller of claim 4, wherein the second logiccircuitry includes a third counter to be clocked by the firstsynchronization signal, and the second logic circuitry is to generatethe second synchronization signal based on the third counter.
 6. Thedisplay controller of claim 5, wherein the second logic circuitry is toreset the third counter based on the base clock.
 7. The displaycontroller of claim 6, wherein the second logic circuitry is to:generate a first reset signal to reset the first counter and the secondcounter; and generated a second reset signal to reset the third counter,the second reset signal different from the first reset signal.
 8. Thedisplay controller of claim 2, wherein the clock generator is togenerate the modulated clock based on the base clock and a referenceclock different from the base clock.
 9. A system comprising: a display;memory to store video data; first logic circuitry to be clocked by amodulated clock, the first logic circuitry including a first counter tobe clocked by the modulated clock, the first logic circuitry to outputan enable signal based on the first counter, the enable signalassociated with transfer of the video data to the display; and secondlogic circuitry to be clocked by a base clock used to generate themodulated clock, the second logic circuitry including a second counterto be clocked by the base clock, the second logic circuitry to output asynchronization signal based on the second counter, the synchronizationsignal to define a horizontal line access cycle, the second logiccircuitry to reset the first counter and the second counter based on thebase clock.
 10. The system of claim 9, wherein the modulated clock is aspread spectrum clock, and the base clock is unmodulated.
 11. The systemof claim 9, wherein the synchronization signal is a firstsynchronization signal and the second logic circuitry is to output asecond synchronization signal based on the first synchronization signal,the second synchronization signal to define a vertical frame accesscycle.
 12. The system of claim 11, wherein the second logic circuitryincludes a third counter to be clocked by the first synchronizationsignal, and the second logic circuitry is to generate the secondsynchronization signal based on the third counter.
 13. The system ofclaim 12, wherein the second logic circuitry is to reset the thirdcounter based on the base clock.
 14. The system of claim 13, wherein thesecond logic circuitry is to: generate a first reset signal to reset thefirst counter and the second counter; and generated a second resetsignal to reset the third counter, the second reset signal differentfrom the first reset signal.
 15. The system of claim 9, furtherincluding a clock generator to generate the modulated clock based on thebase clock and a reference clock different from the base clock.
 16. Amethod comprising: modulating a base clock to generate a modulatedclock; generating, with first logic circuitry clocked with the modulatedclock, an enable signal associated with transfer of video data to adisplay, the enable signal generated based on a first counter includedin the first logic circuitry, the first counter clocked with themodulated clock; generating, with second logic circuitry clocked withthe base clock, a synchronization signal to define a horizontal lineaccess cycle, the synchronization signal generated based on a secondcounter included in the second logic circuitry, the second counterclocked with the base clock; and resetting the first counter and thesecond counter based on the base clock.
 17. The method of claim 16,wherein the modulated clock is a spread spectrum clock, and the baseclock is unmodulated.
 18. The method of claim 16, wherein thesynchronization signal is a first synchronization signal, and furtherincluding generating, with the second logic circuitry, a secondsynchronization signal based on the first synchronization signal, thesecond synchronization signal to define a vertical frame access cycle.19. The method of claim 18, wherein the generating of the secondsynchronization signal includes generating the second synchronizationsignal based on a third counter included in the second logic circuitry,the third counter clocked with the first synchronization signal.
 20. Themethod of claim 19, further including resetting the third counter basedon the base clock.
 21. The method of claim 20, wherein the resetting ofthe first counter and the second counter includes generating a firstreset signal to reset the first counter and the second counter, and theresetting of the third counter generating a second reset signal to resetthe third counter.